China's Silicon Double Breakout: Ascend Inside, CXMT Below
Two markets, one strategy. In the past three weeks China has produced, in sequence, the chip that flipped its AI accelerator market and the memory design that just knocked 10% off the world's leading HBM maker in a single day. The first is Huawei's Ascend 950, launched in March 2026, behind which Morgan Stanley now places 62% of China's AI accelerator market with Nvidia's share effectively at zero. The second is CXMT's 4F² DRAM, a cell architecture "key progress" on which was announced at a Shanghai conference on 9–10 October — and which sent SK Hynix down more than 10% and Samsung 7.4% before a single CXMT die had been shipped to a customer.
They look like separate news stories — an accelerator company and a memory company. They are one story. The same export controls created both, the same software-and-hardware substitution logic runs through both, and the same foundry line in Shanghai caps both. This is the inside view: the dies, the cells, the economics, and the one bottleneck that still decides everything.
Part I — The accelerator flip: Ascend 950
When Washington banned the H20 (the deliberately cut-down Hopper variant) in April 2025, Nvidia took a US$4.5B inventory charge and every serious Chinese AI company lost its legal supply of Western accelerators overnight. Beijing answered with a managed market: a "Xinchuang" procurement list for AI accelerators (initially Huawei and Cambricon only), then an "Anke" security-certification category in May 2026 covering nine domestic chips across seven vendors. Nvidia sits on neither list. Chinese firms did not stop needing silicon; they were told which silicon was sanctioned — and that single decision turned a decade-old domestic chip sector into the fastest-growing hardware market on Earth.
Ascend-class NPU: compute tile grid on a silicon die, flanked by memory stacks.
At the centre of it sits the Ascend 950 generation — two products off one shared die. The 950PR ("Prefill & Recommendation") targets the prefill phase of LLM inference and recommendation systems; the 950DT ("Decode & Training"), due by end of 2026, targets decode and training. Both use third-generation DaVinci cores, but the 950 is the first real architectural departure from the 910 series:
| Feature | Ascend 950 (PR/DT) |
|---|---|
| Compute (PR, claimed) | ~1 PFLOPS FP8 / ~2 PFLOPS FP4 (1.56 PFLOPS FP4 on the Atlas 350 card) |
| Numerical formats | FP8, MXFP8, MXFP4, plus Huawei's own HiF8 dynamic-width float |
| Memory | HiBL 1.0 (high-density, low-cost) or HiZQ 2.0 (high-bandwidth) |
| On-card memory | 112 GB (up to 128 GB / 1.6 TB/s on the 950PR) |
| Interconnect | LingQu 2.0, up to 2 TB/s bidirectional (~2.5x the 910 series) |
| Core design | SIMD + SIMT hybrid, 8:1 Cube:Vector ratio with Cube-Vector fusion |
| Memory access granularity | 128-byte sector cache (down from 512 bytes) |
| Foundry/process | SMIC N+3 (claimed ~5nm-class) |
| Card power | 600 W (Atlas 350) |
Three choices matter more than headline TFLOPS. First, FP4 before Nvidia's Blackwell mainstreamed it: the 950PR is the first domestic Chinese accelerator optimised for 4-bit inference, fitting larger models into less memory at lower cost. Second, HiBL 1.0 is Huawei's first in-house HBM — de-risking a supply chain where the West still has a stranglehold. Third, the SIMD+SIMT hybrid with 128-byte sector caching targets the sparse, irregular memory access patterns of modern MoE architectures, where 910-series chips wasted bandwidth.
The PR/DT split is not marketing theatre; it reflects where the money in inference lives. Prefill (process the prompt) is compute- and bandwidth-hungry and happens in parallel bursts; decode (generate tokens) is latency-bound and token-by-token. Huawei tuned the 950PR's memory stack for prefill throughput and the 950DT for decode bandwidth — the same trick Nvidia plays with Hopper SKUs, applied deliberately to the Chinese workload mix.
The pricing pressure is real. The Atlas 350 card lists at roughly ¥111,000 (US$16,000), and Huawei claims 2.87x the per-card performance of the H20 it replaces. That claim deserves scepticism — Hopper-class silicon does not support FP4 natively, so the comparison is partly format-favoured — but it does not need to be exact to be disruptive. At rack scale it gets serious: the Atlas 950 SuperCluster arrays 8,192 Ascend chips for ~8 exaflops of FP8, and Huawei Cloud has been selling a 1,024-chip Ascend 950 cluster cloud service (1 exaflop FP8, 256 TB pooled) in China since 30 September 2026.
The software war is the real disruption
Hardware gets the headlines; software is what threatens Nvidia. Every framework, pretrained model and research lab assumes CUDA. That lock-in — two decades deep — is the moat the West assumed was unassailable. Huawei's answer is CANN Next, a CUDA-compatible environment that introduces a SIMT programming model over Ascend hardware: keep CUDA as the interface standard while replacing the implementation behind it.
DeepSeek is the proof case — its V4 was co-designed with Ascend and shipped in July 2026 fully adapted for CANN, and "Day-0 adaptation" (a model running on domestic silicon the day it is released) has become the new competitive bar. We covered that co-design in DeepSeek V4: open model, Huawei NPU. When Zhipu open-sourced GLM-5.2 in June, Biren announced Day-0 adaptation within a day.
But the caveat your feed will skip: the software story is unfinished. DeepSeek's earlier attempt to train R2 on Ascend 910C — government-pushed — failed repeatedly and training reverted to Nvidia. The Chinese stack wins at inference today, loses at frontier training. The 950DT and the 2027 Ascend 960 (960DT in Q1, 960PR in Q3) exist to close that gap — see our look at Huawei's broader compute architecture for the family context.
Part II — The memory break: CXMT's 4F²
Now the second half of the story, and the one that moved markets this week. On 9–10 October, at the fourth Integrated Circuit and Chiplet Conference in Shanghai, CXMT president Cao Kanyu reported "key progress" on a 4F² memory cell — a layout Samsung and SK Hynix have been chasing for years — and said the first product, a server DDR5 RDIMM, ships by the end of 2026. Comments confirmed by a company spokesperson to Bloomberg. The result, carried by SCMP, CNBC and the Korean press: SK Hynix down more than 10%, Samsung down 7.4%, both at their lowest since August, Micron off around 4% in pre-market.
What did CXMT actually claim? Three things, all verifiable:
- The 4F² cell — each DRAM cell (one capacitor, one access transistor) squeezes into four square F (F = minimum feature size) instead of the industry-standard 6F²: roughly a 33% footprint cut and a corresponding gain in bits per wafer, the unit that decides DRAM cost per bit.
- A proprietary Vertical Surrounding Gate (VSG) transistor — the access transistor's channel stands upright with the gate wrapped around it, cutting the leakage that has historically capped cell scaling, and freeing the floor space to hit 4F².
- Wafer-level hybrid bonding — memory cells and peripheral CMOS are built on separate wafers and joined with copper, so each can be optimised independently. CXMT says it started this in 2019, has done 12-inch wafer bonding, and holds 300+ patent families in 4F² — mainland China's first 4F² paper was published in 2021, and an 8 Gb full-array test chip appeared at IEDM 2023.
It is a real research pedigree — the IEDM demos and patent families are documented, not claimed. But the market reacted to a promise, and every independent source is careful about the gap between the two. CXMT has published no speeds, no capacities, no yields, no process node, no named customers, and has not posted its own press release. "Two years ahead of Samsung" — the framing in the Seoul press — compares CXMT's launch date with Samsung's 2028 mass-production target: different milestones. South Korean industry officials put the overall technology gap at about three years and asked, bluntly, "who would even buy it?" Morningstar's Jing Jie Yu calls commercialisation "extremely difficult" given uniformity problems in mass production.
That 10% is the real disruption the market already priced in before 4F². CXMT's global DRAM revenue share has gone from 1.8% in 2022 to ~10% in Q2 2026 (fourth place behind Samsung's 38%, SK Hynix's 25%, Micron's 21%), squeezing SK Hynix down 14 percentage points in a year. Its fifth-generation G5 platform is in volume production — an 11.95 nm active-area half-pitch achieved with quadruple patterning and no EUV — and it has matched Samsung's LPDDR6 timeline. Capacity is forecast to hit ~350,000 wafers a month by year-end, near Micron's level.
HBM-style stack: DRAM dies joined by copper microbumps over a logic die and substrate.
The densest irony of the CXMT plan: it skips LPDDR (the easy win) to go straight at server DDR5 RDIMM 24/7 reliability — the hardest segment, and exactly where the verification gap bites. A showcase RDIMM in December is not volume supply in December, and nobody outside CXMT has touched the silicon.
Where the two halves meet: the one fab and the one memory frontier
The link between the two stories is the supply chain that caps both. China's SMIC advanced-node line (N+2) can make roughly 2.6 million AI chips a year against domestic demand near 4.2 million, and Huawei has already locked in about 43% of that capacity. It is not chip design that caps Chinese AI compute — it is a place in a queue at a single foundry line, plus the memory that every one of those accelerators needs.
And memory is where CXMT becomes the system's lynchpin. HBM starts life as DRAM dies; every accelerator order is a memory order. CXMT's HBM3E is at risk-production stage (mass production no earlier than 2027), and Alibaba's T-Head and Cambricon are already evaluating it against their own accelerators — while Huawei's Ascend line is a documented CXMT customer. The binding constraint on China's AI stack runs through two chokepoints at once: the chips queue for wafer starts at SMIC's N+2 line, and the HBM those same chips need waits on CXMT's yield curves — one silicon company can't fix either.
What to watch
The disruption window is real but narrow on both sides, and the tests are calendar-bound:
- Q4 2026 — Ascend 950DT training silicon; CXMT's DDR5 RDIMM reveal (speeds, capacity, a named qualifying customer, any yield number).
- Q1 2027 — T-Head's Zhenwu V900 mass production (216 GB, 1.2 TB/s inter-chip, FP8/FP4, 500K-chip clusters); Alibaba's Qwen 4 in training.
- 2027 — Huawei's Ascend 960 (960DT then 960PR); CXMT HBM3E volume.
- 2028 — Samsung's 4F² mass-production target (its vertical-channel line has been quietly split off as "D0a-V" with no committed date).
Two things would change my read. First, a successful frontier training run on 950DT or 960 — the current stack is inference-confirmed and training-unproven. Second, whether CANN Next, SAIL and MUSA converge or fragment: a fragmented Chinese software ecosystem is the one outcome that hands the CUDA moat its continued existence.
The single most accurate summary of the week comes from the engineers, not the traders: the architecture is real, the patents are real, the dates match — but 30% denser cells on a slide is not 30% cheaper memories in a server, and a 2.87x benchmark claim is not a shipped fleet. The markets repriced both possibilities in 48 hours. The products get to prove them before the year is out.
FAQ
How big is Huawei's share of China's AI accelerator market?
Morgan Stanley estimates Huawei holds about 62% of China's AI accelerator market in 2026, with Nvidia's share effectively zero after the H20 ban. Cambricon is second at roughly 14%, followed by Baidu and Alibaba at about 5% each.
What is a 4F² DRAM cell and why does it matter?
A 4F² cell fits one DRAM cell (a capacitor plus an access transistor) into four square F units instead of the industry-standard 6F², cutting cell footprint by roughly a third and raising bits per wafer. CXMT announced “key progress” on it in October 2026, with a first server DDR5 RDIMM by end of year.
Is CXMT really ahead of Samsung on 4F² DRAM?
CXMT targets a 4F² product (server DDR5 RDIMM) by end-2026, versus Samsung's 2028 mass-production target, so it may ship first. But CXMT has published no specs, yields or named customers, and analysts call commercialisation extremely difficult given uniformity problems.
Disclosure: performance and yield figures above are vendor claims unless indexed to a third-party teardown (TechInsights) or market report (Morgan Stanley, IDC, Omdia, Counterpoint, SemiAnalysis). Treat "2.87x the H20", "8 exaflops" and CXMT's 4F² density as directional, not audited.